The present invention relates to integrated circuit development, and more specifically to translation of electronic schematic files between computer aided software design tools.
Computer-aided design of integrated circuits typically occurs in a multi-tool environment and may be generally divided into a front-end design phase and a back-end development phase, as shown in FIG. 1. During the front-end phase, the engineer user designs and develops, from a set of specifications, a logical representation of the integrated circuit of interest in the form of a schematic, at step 10. The schematic is then entered into a computing platform to generate a circuit netlist, at step 12. To that end, the computing platform includes computing hardware and one or more software tools, e.g., software applications. The netlist defines the entire integrated circuit, including all components and interconnections. Alternatively, the integrated circuit information may be developed using hardware description language (HDL) and synthesis. With the aid of integrated circuit test tools available to the computing platform, the user tests the design of the integrated circuit, at step 14. For example, the operation of the integrated circuit design may be emulated. The integrated circuit design test process may involve several iterations of design modifications and improvements until the integrated circuit design is finalized.
The back-end development involves several steps during which a final circuit layout (physical description) is developed based on the schematic. During placement step 16, various building blocks (or cells) as defined by the finalized integrated circuit schematic are placed within a predefined floor plan. For integrated circuit designs based on array or standard cell technology, the various circuit building blocks are typically predefined. As a result, each cell may correspond to one or more electrical functions, e.g., resistor, capacitor, differential operational amplifier, J-K flip-flop and the like. Placement is followed by a routing step 18, during which interconnects between cells are routed throughout the layout. Finally, the accuracy of the layout versus the schematic is verified at step 20. To that end, the design rules are verified by calling a file on the server that tests the different aspects of the integrated circuit design against different design criteria. For example, the electrical performance of the electrical functions corresponding to the cells employed may be tested. Were no errors or design rule violations found, at step 22, the circuit layout information would be used for the process of fabrication at step 24.
As standard in the computing industry, a wide variety of computing software tools to design integrated circuits exists. Often, the data generated by one software tool is not compatible for use with other software tools. For example, the Composer Tool format from Cadence Design Systems is not compatible with Mentor Graphics GDT format. As a result, considerable time and effort is required to translate, or convert, data between software tools.
To facilitate data conversions, software tools are designed to interpret data in one or more common formats that may be interpreted by all computing software tools, albeit not efficiently. An example of a common format is the electronic design interchange format (EDIF). In this manner, data exchange between first and second software tools occurs through the common format. For example, a first software tool converts data from a first domestic format, which is interpreted by the first software tool, to the common format. A second computing platform then interprets the common format data and converts the same to a second domestic format for interpretation by the second software tool.
Many utility applications exist that allow data conversions between two different software tools. However, many of these utility applications do not accurately convert the entire contents of data files. A need exists; therefore, to provide a method, and system and a computer product, to facilitate translation of electronic schematic files between computer-aided integrated circuit software design tools without losing information in the translation.
The present invention provides a method, a system and a computer product to translate electronic schematic files between computer-aided software design tools. One embodiment of the invention includes converting source files, containing electronic schematic information, into output files. Creating, from the source files, export files that omit a sub-portion of the schematic information, defining omitted data, with each of the export files having a file name associated therewith. Appending, to the file name of the export files, data concerning the omitted information to form an appended file name. The export files are converted to the output files and retain the appended file name. The appended name is diminished so as to remove all information therefrom, excepting information corresponding to the omitted information.